FIG. 1 is a schematic diagram of an exemplary circuit 100 that may be used to drive an external circuit load based on a data signal output by a logic circuit. For example, as shown in FIG. 1, a driver circuit 102 may receive a logic circuit output signal DATA_OUT at node 113, a HIGH source signal voltage VDD, e.g., 3.3 volts, and a LOW source signal VSS, e.g., 0.0 volts, and may generate a node 129 a driver circuit output signal SIG_OUT. Node 129 may be connected via a transmission line 168 to a node 131 within another circuit. In this manner, driver circuit output signal SIG_OUT may be received at node 131 as signal FAR_SIG_OUT and may drive a load 170, e.g., 5 pF, placed between node 131 and ground GND.
FIG. 2 is a more detailed schematic diagram of exemplary circuit 100 described above with respect to FIG. 1. As shown in FIG. 2, driver circuit 102 may include a level shifter 144, first inverter 112, p-type transistor 114, second inverter 116, and n-type transistor 118. One of a source and drain of p-type transistor 114 may connect to HIGH source signal voltage VDD and the other of the source and drain of p-type transistor 114 may connect to driver circuit node 129. One of a source and drain of n-type transistor 118 may connect to driver circuit node 129 and the other of the source and drain of n-type transistor 118 may connect to a LOW source signal voltage VSS. An input lead of level shifter 144 may connect to node 113 and an output lead of level shifter 144 may connect to an input lead of first inverter 112 and an input lead of second inverter 116. An output lead of first inverter 112 may connect to the gate of p-type transistor 114, and an output lead of second inverter 116 may connect to the gate of n-type transistor 118.
As further shown in FIG. 2, driver circuit 102 may be implemented on a periphery of a first integrated circuit 101. For example, driver circuit 102 may connect via the input lead of level shifter 144 at node 113 to a logic circuit (not shown) implemented on first integrated circuit 101. Further, driver circuit 102 output node 129 may connect to a pad 167 on first integrated circuit 101.
In operation, driver circuit 102 may receive logic circuit output signal DATA_OUT, a node 113, from the logic circuit within first integrated circuit 101, and may generate a driver circuit output signal SIG_OUT that may be delivered to pad 167 of first integrated circuit 101. A transmission line 168 may transmit driver circuit output signal SIG_OUT to an input pad 169 at node 131 of a second integrated circuit 103 to drive a load. For example, as shown in FIG. 2, signal SIG_OUT may be used to drive a 5 pF load 170 within second integrated circuit 103. Such a load may be due to a receiver circuit on second integrated circuit 103 that may be configured to receive and use signal SIG_OUT in subsequent operations. In this manner, driver circuit 102 may facilitate communication between various integrated circuits in an electronic system.
Although the circuit described above with respect to FIG. 2 may be used to implement an integrated driver circuit that facilitates communication between integrated circuits, such driver circuits suffer from inefficiencies such as the inability to drive heavy loads and crowbar currents. A crowbar current is a sudden surge of current flowing from a high voltage source to ground as a result of the rapid ON and OFF switching of transistors along a circuit path between the high voltage source and ground. For example, in the circuit presented in FIG. 2, internal transistor delays may result in a condition in which p-type transistor 114 remains ON temporarily as it is being turned OFF while n-type transistor 118 is being turned ON. This may result in a sudden surge of current flowing from high signal source VDD to low signal source VSS creating what is commonly known as crowbar current.
For example, assuming that logic circuit output signal DATA_OUT is initially LOW, the inverted signal at node 115 is HIGH, the inverted signal at node 123 is HIGH, p-type transistor 114 is OPEN, i.e., in a non-conducting state, and n-type transistor 118 is CLOSED, i.e., in a conducting state. Therefore, driver circuit output signal SIG_OUT is LOW. However, as signal DATA_OUT begins to rise and the inverted signal at node 115 falls to a threshold voltage of p-type transistor 114, p-type transistor 114 may CLOSE, while n-type transistor 118 is still CLOSED. Therefore, a crowbar current passes from HIGH signal source VDD to LOW signal source VSS.
Further, assuming that logic circuit output signal DATA_OUT is HIGH, as signal DATA_OUT begins to lower and the inverted output signal of transistor 116 at node 123 rises above a threshold voltage of n-type transistor 118, n-type transistor 118 may CLOSE, while p-type transistor 114 is still CLOSED. Therefore, a crowbar current may again pass from HIGH signal source VDD to LOW signal source VSS.
Such crowbar currents result in a wasteful dissipation of power. In an integrated circuit with a large number of integrated circuits, the cumulative loss of power due to crowbar currents may be significant. Further, during the period when both n-type transistor 118 and p-type transistor 114 are both on there may be a contention over the voltage at node 129 and driver circuit output signal SIG_OUT. This contention may add to and amount of time required to switch the value of signal SIG_OUT, i.e., may add to the total delay through the driver circuit.